Field
The present disclosure relates generally to the design of integrated circuits, and more particularly, to power grid design for the central processing unit (CPU) subsystem.
Background
Semi-conductor apparatuses, such as integrated circuits, are constructed from electronic components formed on semiconductor materials and interconnected with circuit wiring. A network of these circuit wirings may connect a group of components and provide the components with power at a particular voltage level. Power grid (power distribution network) generally refers to the networks of circuit wirings which connect power supply to each component. Power grid design includes the analysis and design of such networks.
An integrated circuit (IC) may have more than one group of components, where each group of components is designed to operate at a different voltage level. For example, a first group of components may be designed to operate at a first voltage level, and a second group of components may be designed to operate at a second, different voltage level. Integrated circuits that are designed with groups of components operating at more than one voltage level are said to have multiple power domains, where each power domain is associated with a particular voltage level. In operation, a particular power domain may be selectively powered up or down by controlling power to the network of circuit wirings connecting the group of components in that power domain.
Because memory circuits and logic circuits have different voltage requirements, memory circuits and logic circuits usually reside in different power domains. CPU cache memory is one type of memory circuit. Thus, CPU cache memory resides in the memory power domain with other types of memory circuits. The memory power domain generally sources its power from a power supplier that is shared by several other components that may have higher voltage requirement than the CPU cache memory. In order to support those other components, the shared power supplier needs to maintain a higher voltage level than the CPU cache memory requires. This leads to significant power inefficiency for CPU cache memory.